1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to dielectric structures having a relatively low dielectric constant arranged adjacent to the opposed lateral edges of a trench isolation structure to enhance the reliability of the integrated circuit employing the dielectric structures.
2. Description of the Relevant Art
The fabrication of an integrated circuit involves forming numerous devices in active areas of a semiconductor substrate. Select devices are interconnected by conductors which extend over a dielectric that separates or "isolates" those devices. Implementing an electrical path across a monolithic integrted circuit involves selectively connecting devices which are isolated from each other. When fabricating integrated circuits, it is therefore necessary to isolate devices built into the substrate from one another. From this perspective, isolation technology is one of the critical aspects of fabricating a functional integrated circuit.
A popular isolation technology used for a MOS integrated circuit is a technique known as the "shallow trench process". Conventional trench processes involve the steps of etching a silicon-based substrate surface to a relatively shallow depth, e.g., between 0.2 to 0.5 microns, and then refilling the shallow trench with a deposited dielectric. The trench dielectric is then planarized to complete formation of a trench isolation structure in field regions of the substrate. The trench isolation structure is formed during the initial stages of integrated circuit fabrication, before source and drain implants are placed in device areas or active areas. Trench isolation processing serves to prevent the establishment of parasitic channels in the field regions between active areas. The trench process is becoming more popular than the local oxidation of silicon process ("LOCOS"), another well known isolation technique. The shallow trench process eliminates many of the problems associated with LOCOS, such as bird's-beak and channel-stop dopant redistribution problems. In addition, the trench isolation structure is fully recessed, offering at least a potential for a planar surface. Yet further, field-oxide thinning in narrow isolation spaces is less likely to occur when using the shallow trench process.
While the conventional trench isolation process has many advantages over LOCOS, the trench process also has several problems. A technique known as "lithography" is used to pattern a photosensitive film (i.e., "photoresist") above the region of the substrate to be etched to form the trench. An optical image is transferred to the photoresist by projecting a form of radiation, primarily ultraviolet light, through the transparent portions of a mask plate. The solubility of regions of the photoresist exposed to the radiation is altered by a photochemical reaction so that those regions may be removed when washed with a solvent. In this manner, the portions of the substrate to be removed are exposed while those portions to be retained are protected by the photoresist which remains intact during the etch step. The lateral width (i.e., the distance between opposed lateral edges) of the trench is thus mandated by the lateral width of an overlying photoresist layer. Unfortunately, the minimum lateral dimension that can be achieved for a patterned photoresist layer is limited by, inter alia, the resolution of the optical system (i.e., aligner or printer) used to project an image onto the photoresist. The term "resolution" describes the ability of an optical system to distinguish closely spaced objects. The resolution of modern aligners is mainly dependent upon diffraction effects in which radiation passing past an edge or through a slit on a masking plate spreads into regions not directly exposed to oncoming waves. As such, the features patterned upon a masking plate may not be correctly printed onto photoresist. The images projected onto photoresist may have larger dimensions than their corresponding features on the masking plate.
Since trench formation involves etching the silicon substrate, it is believed that dangling bonds and an irregular grain structure form in the silicon substrate near the walls of the trench. In a subsequent processing step, the active areas of the semiconductor substrate may be implanted with impurity species to form sourcetdrain regions therein. The semiconductor topography may be subjected to a high temperature anneal to activate the impurity species in the active areas and to annihilate crystalline defect damage of the substrate. Unfortunately, impurity species which have a relatively high diffusively, such as boron, may undergo diffusion into the isolation region when subjected to high temperatures. The irregular grain structure may provide migration avenues through which the impurity species can pass from the active areas to the trench isolation structures. Moreover, the dangling bonds may provide opportune bond sites for difflusing impurity species, thereby promoting accumulation of impurity species near the edges of the isolation structures.
It is postulated that the presence of foreign atoms within a trench isolation structure may result in that structure having a relatively high defect density. For example, clusters of foreign atoms may cause dislocations to form in close proximity to the lateral edges of the trench isolation structure. It is believed that the voltage required to cause dielectric breakdown of a trench isolation structure decreases as the defect density (or doping density) within the isolation structure increases. Consequently, when a voltage is applied across a conductor arranged horizontally above the trench isolation structure, dielectric breakdown may occur in those areas of the isolation structure having a high defect and/or doping density. In particular, the configuration of a local interconnect above a trench isolation structure may lead to breakdown at the edges of the isolation structure. Local interconnects are relatively short routing structurcs, and can be made of numerous conductive elements, e.g., doped polysilicon, or reacted polysilicon ("polycide"). As a result of placing a local interconnect in a misaligned contact opening, current may undesirably pass through the trench isolation structure in close proximity to its edges, electrically linking an overlying local interconnect to the bulk substrate. Furthermore, the threshold voltage near the lateral edges of the trench isolation structure may be reduced, and current may inadvertently flow (i.e., leak) between isolated active areas.
FIG. 1 depicts a cross-section of a semiconductor topography in which a local interconnect 34 extends horizontally above a semiconductor substrate 10 upon and within which are formed transistors 12 and 14. Local interconnect 34 serves to couple a gate conductor 16 of transistor 12 to a source/drain region 22 of transistor 14. This form of coupling is prevalent in, for example, high density VLSI logic and SRAMs. A source/drain region 20 of transistor 12 is isolated from the source/drain region 22 of transistor 14 by a trench isolation structure 24 comprising silicon dioxide ("oxide"). Local interconnect 34 is spaced above substrate 10 by an interlevel dielectric 30 comprising oxide. A conductive contact 32 known as a "buried contact" extends through interlevel dielectric 30 and forms electrical contact between local interconnect 34 and source/drain region 22. Formation of contact 32 may involve etching an opening vertically through interlevel dielectric 30 using conventional optical lithography techniques and, e.g., a plasma etch technique highly selective to the oxide-based interlevel dielectric 30. Unfortunately, misalignment of the photoresist masking layer used to define the opening may occur during optical lithography. As a result of misalignment, a portion of the oxide-based trench isolation structure 24 near the lateral edge of the structure may be removed before complete termination of the etch. Thus, when a conductive material is deposited into the opening to form contact 32, it may become arranged slightly over the peripheral portion of trench isolation structure 24 that was removed during contact etch. The presence of the conductive material at the comer region of isolation structure 24 may cause unacceptable current leakage between source/drain region 20 and source/drain region 22 during the operation of the ensuing integrated circuit.
It would therefore be desirable to develop a technique for forming a trench isolation structure which would be resistant to breakdown when a voltage is applied across a conductor positioned above the isolation structure. Such a trench isolation structure would be less likely to experience current leakage and would properly isolate the active areas which it separates. It would also be beneficial to devise a trench isolation structure that would withstand removal when an overlying interlevel dielectric is being selectively etched. A misaligned contact formed partially upon the trench isolation structure would be less likely to extend down into the structure where it could give rise to unwanted current leakage between the active areas. Yet further, a process is needed in which the minimum lateral width of the isolation structure is not limited by the minimum achievable lateral width of photoresist patterned using optical lithography. Reducing the lateral width of the trench isolation structure would allow for increased circuit complexity and integration density.